An entangling gate for dual-rail erasure qubits

To progress from the present-day era of NISQ machines¹⁴ to the era of effective quantum error correction (QEC), the performance of physical qubits and their fundamental operations must improve markedly. A useful approach to relax the requirements for QEC is to engineer qubits with structured noise, in which certain types of errors occur much more frequently than others, and to adapt the QEC scheme accordingly to take advantage of this noise. This strategy works best when the error structure is preserved as much as possible throughout all gates and measurements.

Stabilized cat qubits are an example of this model^{15,16,17,18,19,20}, in which bit flips can be greatly suppressed relative to phase flips then allows us to concatenate these physical qubits with a repetition¹⁸ or thin rectangular surface code^{8,21,22,23,24} for a substantially improved QEC encoding rate.

A second way to realize this model is with erasure qubits, in which most of the errors can be detected as they occur at the hardware level¹⁰. After resetting these faulty qubits, the resulting error channel resembles a Pauli error at known spacetime location—an erasure error. QEC codes are generally more tolerant to erasures and can generally correct for twice as many erasures as Pauli errors at a given code distance⁵. They also possess higher thresholds as demonstrated by the surface code, which has a threshold close to 25% for phenomenological erasure noise^12,13.

Erasure qubits are most often realized by detecting loss events that take us out of the computational subspace. For dual-rail qubits, such as those in photonic^25,26,27,28 or superconducting platforms, this is loss of a photon or excitation that takes us to the vacuum state. In other platforms, such as neutral atoms or trapped ions, leakage to non-computational states or loss of the atom from the trap can also be detected and converted to an erasure^10,29,30, with similar benefits^9,31.

In superconducting circuit platforms, dual-rail qubits can be realized with pairs of transmons^6,32,33,34 or microwave cavities^7,35,36. When idling, dual-rail cavity qubits exhibit a strong hierarchy of errors that make them a promising erasure qubit. In this hierarchy, erasures dominate by a factor of 5–10 compared with phase flips, whereas the remaining bit flips are exceedingly rare. So far, superconducting dual-rail cavity qubits have demonstrated fast, high-fidelity single-qubit gates^37,38, good state preparation and measurement (SPAM)³⁶, and efficient, non-destructive detection of erasures^39,40. However, a vital missing ingredient is an entangling operation between two dual-rail qubits, which must simultaneously have low error rates and preserve the favourable error hierarchy.

Here, we propose and experimentally demonstrate a controlled-Z (CZ) operation that satisfies these requirements for dual-rail cavity qubits. Our so-called ‘Swap–Wait–Swap’ (SWS) gate uses high-fidelity parametric operations to temporarily swap an excitation from one of the cavities (that comprise the dual-rail ‘control’ qubit) to a transmon coupler connecting the two dual-rail qubits, similar to the scheme in ref. ⁴¹. By temporarily populating the coupler, we are able to use the strong (MHz level) dispersive shift between the coupler and a cavity of the other (‘target’) dual-rail qubit. Swapping the excitation back into the control cavity completes the gate, allowing us to realize a CZ entangling gate in about 500 ns.

Importantly, our gate is bias-preserving in several aspects. The excitation-preserving nature of the gate preserves the erasure-to-Pauli noise bias on both qubits, with erasure rates below 1%. After erasure detection, we find the residual dephasing errors are at or below 0.1% per gate, as characterized by quantum state tomography (QST) and interleaved randomized benchmarking (IRB). Moreover, we also observe a strong Pauli noise bias in our gate with bit-flip errors at the order of 10⁻⁶ per CZ gate, an advantageous bias first explored theoretically in ref. ¹¹. Moreover, target qubit erasures and dephasing rates are a factor of 3–4 times lower than those for the control qubit. This asymmetry can be carefully managed when detecting error syndromes in a QEC context (J.D.T., manuscript in preparation) to ensure errors on data qubits are minimized. Finally, we study the error channel when one of the qubits suffers from photon loss during or before the gate, and show both theoretically and experimentally that this amounts to a conditional-dephasing error on the other qubit. All of these properties can be exploited by properly designed error correction codes, as we show with simulations in the surface code (Methods). The performance levels we demonstrate are well past the predicted surface code thresholds obtained from simulations¹⁰ (J.D.T., manuscript in preparation) and should thus allow significant logical error suppression with increasing code distance.

Our two-qubit gate makes use of a dispersive interaction to implement a CZ gate between two dual-rail qubits, each comprising a pair of nominally linear microwave cavities. For dual-rail cavity qubits, enacting a CZ gate in the Fock basis between two cavity modes (one from each dual-rail qubit) also enacts a CZ gate in the dual-rail basis.

Thus, nearest-neighbour coupling of the cavities is sufficient to implement a dual-rail CZ gate. The physical system shown in Fig. 1a realizes this by using a coupler c to enact a CZ gate on the adjacent a₂ and b₁ cavities. The dispersive interaction we use for this purpose acts between the coupler and cavity mode b₁ in the target qubit, \({{\mathcal{H}}}_{{\rm{int}}}/h={\chi }_{bc}{\widehat{b}}_{1}^{\dagger }{\widehat{b}}_{1}{\widehat{c}}^{\dagger }\widehat{c}\), where χ_bc/2π = −1.51 MHz in our system.

Normally, this static interaction term does not affect the system dynamics in any way, and is effectively ‘switched off’ since the coupler mode c is in its ground state. The interaction can be effectively switched on by attempting to swap a photon between the cavity a₂ and coupler c, temporarily redefining the control dual-rail qubit between the non-local elements a₁ and c (Fig. 1b). Such a swap here is implemented using a parametric sideband interaction between the coupler and cavity: \({\mathcal{H}}/\hbar =\frac{{g}_{ac}}{2}({\hat{a}}_{2}^{\dagger }\hat{c}+{\hat{a}}_{2}{\hat{c}}^{\dagger })\), similar to the interaction used to affect single-qubit gates in dual-rails³⁸. In our hardware, g_ac/2π = 4.23 MHz. The dispersive interaction is then allowed to act for a time t ≈ π/χ_bc, thus entangling the two qubits. A final swap between the coupler and cavity a₂ returns the excitation back to the control cavity. The entangling phase ϕ_e = χ_bct_wait has thus been imparted only to the |0,1,1,0⟩ initial basis state (using the notation |a₁,a₂,b₁,b₂⟩), which results in a control-phase gate with phase set by the wait time. We adjust this wait time to realize a CZ gate.

Our gate construction allows us to effectively realize a large ‘switchable’ dispersive interaction between cavity modes a₂ and b₁, without needing to modulate the strength of the underlying static dispersive interactions in our system, which often requires complex Hamiltonian engineering⁴². From this construction, we also expect our gate to exhibit highly structured noise, which is advantageous for QEC syndrome extraction circuits (see the Methods for an example with the surface code and J.D.T., manuscript in preparation).

We now describe this noise structure in detail. The first observation we make is that the total number of excitations are preserved throughout the entire operation. Both control and target dual-rails never leave the single-excitation manifold (redefining the control dual-rail as modes a₁ and c during the gate). This property ensures that any photon loss, even in the coupler mode, leads to a loss error that can be detected after our CZ gate. As an added benefit, we also avoid detrimental effects due to cavity self-Kerr, as no mode is populated with more than one photon at any point during the gate. A caveat, however, is that errors on the target and control qubits can have significant asymmetry. The control qubit, which partially occupies the coupler mode during the gate, experiences increased loss (with probability t/T₁ ≈ 1%) and dephasing (t/T_ϕ ≈ 0.1%) compared with the target qubit (t/T_1,cav ≈ 0.1%, t/T_ϕ,DR ≈ 0.01%), owing to the lower coherence times of the coupler mode compared with the cavities. We term this property of our gate as an error asymmetry. Another property that arises naturally is the strong suppression of bit-flip errors, as observed in the idling state of the dual-rails³⁶. This is because the outer cavities a₁ and b₂ and their couplers remain completely idle during the gate. As such, our gate is bias-preserving to dephasing errors. Finally, we expect well-behaved propagation of leakage errors. The dominant leakage channel is decay to the vacuum state, which switches off the CZ-generating cross-Kerr interaction. Thus, if either of the dual-rails relaxes to vacuum, subsequent CZ gates simply do not occur, as if they were omitted from the quantum circuit.

Our experimental two-qubit system also exhibits high-fidelity SPAM and single-qubit gate fidelities that aid in the detailed characterization of our two-qubit gate. Single-qubit gates are performed by driving a beamsplitter interaction within the dual-rail for durations of about 200 ns, achieving erasure rates of approximately 0.1% and post-selected randomized benchmarking error of about 0.01%. By using end-of-the-line erasure-detected measurements³⁶, we are able to obtain low post-selected SPAM errors of about 0.02%. We provide additional results in Supplementary Information section I. A detailed explanation of these parameters and the calibration protocol can be found in Supplementary Information sections II and XIII.

We now present several methods for characterizing the fidelity and error structure of the SWS gate. As with all operations on erasure qubits, we must carefully quantify both the erasure rate and the residual Pauli errors. We use the SWS gate to generate an entangled Bell state, which we analyse using QST. We also perform IRB to evaluate gate performance in arbitrary circuits.

For our first demonstration of the SWS operation, we show high-fidelity entanglement between two dual-rail qubits by implementing the circuit in Fig. 2a with a single CZ gate (N = 1). As shown in Fig. 2, we generate a high-fidelity Bell state and, after post-selection of erasures, extract an end-to-end circuit state fidelity of 99.60(1)% and a state purity of 99.46(3)%. We highlight that this infidelity of about 0.4% includes errors aggregated from SPAM, single-qubit gates and the CZ gate.

Next, we perform repeated CZ gates that repeatedly entangle and disentangle the two qubits up to N = 103 to establish a more precise metric for the error per CZ gate, using the sequence shown in Fig. 2a. The dependence on the number of gates is shown in Fig. 2c, in which we present state fidelity, state purity and post-selected fraction as a function of the number of repeated CZ gates. First, we can consider the behaviour at lower gate repeats. As shown in Fig. 2c (inset), our data show a linear decrease in fidelity and purity out to N = 15 repeated gates, from which we extract a post-selected infidelity of 0.029(6)% per gate.

We also analyse the results for larger gate depths up to N = 103. First, we extract the post-selected fraction (Fig. 2c, bottom), defined to be the fraction of experimental shots for which no erasures were detected. From fitting the results to an exponential decay, we extract a total erasure probability per CZ gate of 0.53(2)%. As the number of gates increases, both the fidelity and purity of the final state (Fig. 2c, top) exhibit an unexpected approximately quadratic decrease. We propose the cause to be drift in calibration parameters or fluctuations in the frequency of the coupling transmon on timescales of experimental shot averaging. Our results indicate that dynamical decoupling by adding more X gates between CZ gates does not alleviate this effect. Understanding the root cause of this effect will require further investigation. As a conservative bound for the gate error, we consider the error at N = 103 and show the corresponding QST results in Fig. 2b and extract an end-to-end circuit state fidelity of 87.5(1)% and state purity of 78.4(2)%. From this, we infer a bound of 0.12(1)% error per CZ gate, which is among the best reported for superconducting qubits.

As an alternative method for determining the post-selected gate fidelity, we perform IRB to test our CZ gate (Fig. 2d). Because of the finite erasure probability of 0.69(2)% per gate, the usable sequence depth is limited to only a few hundred gates (Fig. 2d, bottom). This complicates the fitting to the typical exponential form expected for sequence yield (Fig. 2d, top). A detailed analysis of gate error extraction can be found in Supplementary Information section IV. We, therefore, use a linear fit at shorter gate depths (Fig. 2d, inset), obtaining an estimate for the error per CZ gate of 0.108(5)% in reasonable agreement with the result from repeated Bell state tomography. See Supplementary Information section V for an analysis on nuanced effects of leakage and seepage errors (leakage states silently re-entering codespace)^43,44. In Supplementary Information section XII, we performed repeated IRB benchmarking for up to 15 h on seven different two-qubit systems, with similar properties to the one characterized here.

Having benchmarked the performance of the CZ gate, we now investigate the structure of gate errors on the control and target qubit and show we preserve the error hierarchy when performing CZ gates. In the following, we measure the error asymmetry for leakage, dephasing and bit-flip errors.

First, we characterize the fraction of detected leakages for our repeated gate Bell state tomography, extracting assigned erasures for the control qubit only, target qubit only, and both qubits, shown in Fig. 3a. As expected, we observe a higher fraction of erasures on the control qubit compared with the target qubit, extracting 0.400(4)% and 0.096(4)% per CZ gate for control and target qubit, respectively. Taken together, this erasure asymmetry of about 4 is consistent with the relative T₁ between the coupler and the average T₁ of the target qubit cavities.

Next, we study the relative fraction of dephasing errors on the control and target qubit. Analysing the reconstructed quantum state from our Bell state tomography, we extract Z errors on the target and control qubit individually as well as correlated ZZ dephasing on both qubits. Our results are shown in Fig. 3b, showing a clear asymmetry in Z errors between the control and target qubit, and small ZZ errors that affect both qubits. From these results, we extract target qubit Z errors of 0.0112(9)% per CZ gate. The control qubit Z errors, however, show the same type of nonlinear behaviour observed for the QST results, suggesting that the root cause of this behaviour could be attributed to some characteristic of the coupler. To quantify the control qubit error, we evaluate at N = 27 gate repeats and extract an averaged Z-error of 0.039(1)% per CZ gate. Using the same analysis, we extract ZZ errors of 0.007(1)% per CZ gate. Overall, we observe a dephasing ratio of about 3.5, which is consistent with what we expect from coupler and dual-rail T_ϕ dephasing times. Detailed simulations of the CZ gate error structure can be found in Supplementary Information section XIV.

Idle dual-rail cavity qubits exhibit extremely low bit-flip errors³⁶, because they require the loss of a photon in one cavity and the gain of a photon in the other (a double error). We expect our CZ gate to also exhibit this property and experimentally confirm only a small increase in bit-flip errors when executing the CZ gate, relative to the idle case, as shown in Fig. 3d. We also further characterize bit-flips on the control and target qubits separately, as summarized in Fig. 3e and Supplementary Information section XI. The total probability of any bit-flip is bounded at a few parts per million per gate, which is probably not limited by ‘true’ bit-flip errors but rather a photon loss event followed by misassigning a leakage error as being in the codespace in the final. Once again, the asymmetry in observed bit-flips on the control and target qubits is in line with what we expect from the lower T₁ of the coupler.

Finally, we investigate how the dominant |00⟩ leakage propagates through the CZ gate while awaiting detection by erasure check measurements. Leakage is typically considered to be a particularly damaging error in a QEC context. If not properly controlled, leakage may propagate without bound, resulting in correlated errors and diminished effective code distance.

In our system, we consider two possible leakage scenarios: photon loss to |00⟩, which occurs before a CZ gate and leakage that occurs midway through the CZ gate at an unknown time. We study the more likely scenario of leakage affecting only the control qubit, although due to the symmetry of a CZ gate, our results are expected to apply similarly to the case of leakage on the target qubit. Although other dual-rail leakage states are possible due to cavity heating, such as |02⟩ or |11⟩, these occur at least 1,000 times less frequently in our hardware and are not considered here.

We can first consider what happens if the control qubit is in the |00⟩ state before the CZ gate. As there is only one excitation in the system (in the target qubit), the dispersive interaction does not affect any system dynamics, resulting in an identity operation on the target qubit. The exact same scenario occurs if the control qubit begins in |10⟩ and suffers from photon loss in mode a₁ during the CZ gate: as no photons were ever swapped into the coupler, the dispersive interaction was never activated, which again results in an identity operation on the target.

The case when the control qubit begins in |01⟩ and swaps into the coupler is more involved. Should excitation loss occur at any time during the gate, the end result is equivalent to performing a CPHASE gate with an unknown rotation angle, and the control qubit ending in vacuum. Averaging over all possible loss times results in what we term a ‘CZ error’, a correlated error in which the target qubit dephases, but only if the control leaks from the initial |01⟩ state.

This type of ‘benign’ leakage propagation can be incredibly useful for QEC, by enabling fewer and delayed erasure checks. For instance, in the surface code, we may perform all erasure checks at the end of a round of syndrome extraction rather than after every two-qubit gate (Methods), without significant loss of threshold or effective code distance. A more detailed and theoretical treatment of this leakage error model can be found in Supplementary Information section VI.

We use quantum process tomography to verify and measure these leakage properties, as shown in Fig. 4c. We prepare the control qubit in the known states |01⟩, |10⟩ and |00⟩ and perform N repeated CZ gates followed by process tomography on just the target qubit. In all cases, we require the control qubit to end in the state |00⟩ and post-select accordingly. Our results (Fig. 4d,e for N = 1 and N = 27 CZ gates) show the expected trivial behaviour when the control qubit begins in |00⟩ or |10⟩ state, and at N = 1, we measure the deviation from the ideal identity channel to be Pauli errors on the target qubit with strength 0.19(2)% and 0.18(2)%, when preparing |00⟩ or |10⟩ in the control qubit, respectively. Repeating the gate many times allows us to reduce the contribution from SPAM errors. At N = 27, we estimate the fraction of CZ erasures to be roughly two-thirds of total erasures, and measure the target qubit Pauli errors to be 0.012(1)% and 0.013(1)%, respectively, per CZ gate.

Finally, tomography for when the control qubit begins in |01⟩ is shown in Fig. 4f. Visually, the process matrix on the target qubit closely matches a pure dephasing channel. More quantitatively, we extract the deviation from the pure dephasing channel: for N = 1 gates, the extracted residual X and Y errors total 0.7(1)%. Similarly, at N = 27, we determine this error to be 0.094(2)% per CZ gate. This can be interpreted as an upper bound on the X and Y Pauli errors on the target when the control qubit leaks from |01⟩ during the gate.

The addition of a fast and high-fidelity entangling operation completes the toolbox of gates and operations for dual-rail cavity qubits⁷. We have experimentally confirmed several properties important for erasure qubits. It preserves (Table 1) the desirable error hierarchy by exhibiting both a strong erasure-to-Pauli noise bias and a dephasing-to-bit-flip noise bias. Furthermore, we observe a significant asymmetry in the errors induced on the control compared with the target qubit. Finally, the gate has a simple error channel in the event that one of the qubit is erased before or during the gate, which is useful for delaying erasure checks in QEC contexts.

Our results present numerous opportunities for operating dual-rail cavity qubits at scale with high-performance: from enabling high-circuit performance for short-depth circuits, to new types of error mitigation through flagging erasures, to—perhaps most excitingly—a viable path for implementing QEC using erasure qubits. As a preview for how well we expect our dual-rail cavity qubits to perform for QEC, in the Methods, we present some preliminary results simulating the performance of a surface code implemented using dual-rail cavity qubits with a more comprehensive treatment in an upcoming publication (J.D.T., manuscript in preparation). We find that even with current CZ gate performance, the error rates are already a factor of ten below the respective erasure and dephasing thresholds. Further improvements in physical error rates can also be straightforwardly achieved through improvements in beamsplitter rates to increase gate speed and through improving the coherences of, primarily, the coupler. In the presence of both kinds of errors, detailed numerical simulations (J.D.T., manuscript in preparation) are needed to estimate the actual performance, but the results described here provide a path to realize large error correction gains of 10 or more with an increase in code distance in the near future. All of these results highlight that superconducting dual-rail cavity qubits have quickly become an attractive path for achieving fault-tolerant quantum computing. During the completion of this paper, we became aware of related work on implementing the two-qubit gates using tunable dual-rail transmon qubits⁴⁵.

Quantum error correction benefits of structured noise in our CZ gate

Our SWS gate possesses an error structure that can be leveraged to reduce errors during syndrome extraction in stabilizer codes such as the surface code. Here, we show simulations using Stim⁴⁷ that support and quantify this claim by studying the reduction in logical error rate compared with code distance in a surface code memory. More complete simulations results and methodology will be the subject of an upcoming, separate publication (J.D.T., manuscript in preparation), which solely focuses on QEC scaling in a dual-rail cavity qubit surface code.

There are four aspects to the SWS gate error structure that are expected to improve syndrome extraction circuits in general:

• Erasures (leakages to |00⟩) occur much more frequently than Pauli errors.

• Pauli errors are mostly dephasing errors; bit flips are rare.

• We can designate the ‘control’ qubit to be the ancilla, which then picks up most of the erasure and dephasing errors, leaving the data qubits mostly error-free.

• Once a qubit has leaked to |00⟩, subsequent CZ gates are skipped, which allows us to perform less frequent erasure checks.

We quantify error correction performance by extracting Λ, the factor by which the logical error rate (per syndrome extraction round) decreases when the surface code distance is increased by 2 (refs. ^3,4). We compare two noise models. The first is a noise model in which only the CZ gates are error prone, and the error rates for all CZ gates are identical to the values shown in the paper at low repeated gate depth, that is, ancilla erasure = 0.4%, data erasure = 0.1%, ancilla dephasing = 0.04%, data dephasing = 0.01%, joint dephasing = 0.01%, ancilla bit flip = 0.0003%, data bit flip = 0.00005%. We also include perfect erasure checks, which are delayed to the end of the syndrome extraction round (see next section in Methods as to why we make this choice). The second noise model uses only a two-qubit depolarizing noise channel after each CZ gate as the only source of error, a well-studied noise model with a threshold close to 1%. For this noise model, we set the error rate p = 0.1% to reflect state-of-the-art performance in other two-qubit gates with ‘unstructured’ errors. Both simulations to extract Λ are performed using Stim. For the first error model, leakage errors cause subsequent CZ gates to be omitted from the simulation (a property confirmed experimentally in Fig. 4), until the qubit is detected and reset, which is crucial for accurately modelling the propagation of leakage errors with delayed erasure checks. The results shown in Extended Data Fig. 1 show Λ ≈ 14 for the depolarizing noise model and Λ ≈ 27 for our SWS gate error model, demonstrating the benefits of structured errors. More detailed analysis can be found in our upcoming publication (J.D.T., manuscript in preparation). We reiterate that these noise models are chosen to be simplistic, to allow direct comparison between the two-qubit gate errors. More realistic simulations must include errors in the single-qubit gates, all measurements (including erasure checks) and idling errors, which reduce the value of Λ.

Leakage propagation and delayed erasure checks in a dual-rail surface code

A key property of our SWS gate is that attempting to perform the gate when one of the qubits has leaked to |00⟩ before the gate results in identity being performed on both qubits, and excitation loss at any point in time during the gate can be accurately modelled as a CPHASE gate of unknown angle (between 0 and π) followed by photon loss on one of the dual-rail qubits. These properties were experimentally verified in Fig. 4. Here, we show with simulations that this property can be leveraged to delay all mid-circuit erasure checks to the end of the syndrome extraction round, without significant loss of code distance or threshold we expect from erasure qubits.

Performing erasure checks once every four CZ gates (rather than after every CZ gate) makes us much less prone to errors in the erasure checks themselves, which is vital for achieving good error correction performance in practice. This also, in principle, enables us to avoid mid-circuit erasure detection entirely in a surface code, by instead detecting erasures by 1-bit Knill-style teleportation in between syndrome extraction rounds⁴⁸ (that is, teleporting back and forth between data and ancilla qubits, and performing a ‘destructive’ erasure check whenever a qubit is measured out in an end-of-the-line measurement). As such, the importance of a high-fidelity, fast mid-circuit erasure check may have been previously overemphasized for erasure qubitsthat possess this ‘leakage skips subsequent gates’ property.

To verify these claims, we perform Stim simulations in which the data qubit and ancilla qubit each have probability p/2 of leaking to the |00⟩ state after every CZ gate, and subsequent CZ gates are skipped (that is, omitted from the quantum circuit) if any one of the qubits in the CZ pair are in |00⟩. We then perform perfect erasure checks at the end of each round. From Extended Data Fig. 2, we extract a threshold of 5.6% and verify preservation of the effective code distance by fitting the logical error rate to the model p_L ∝ p^αd. We find α = 0.93, close to the value of 1 expected for erasure-like errors. For Pauli-like errors, α = 0.5 is expected instead.

The threshold we find is slightly higher than that obtained in ref. ¹⁰, in which a threshold of 5.13% was obtained for an error model with perfect erasure checks after every CZ gate, but also assumed leakage during a CZ gate caused a depolarizing error on the other qubit, which we believe introduces more entropy (and more possible syndromes to decode) than our error model.

When delaying erasure checks to the end of the syndrome extraction round, there is an increased uncertainty with regard to the exact time location of the leakage event in the syndrome extraction gate sequence. However, we find that this added uncertainty does not lead to any bad hook errors. This property can be verified by exhaustively sampling detector flip patterns for all possible locations of a single leakage event in the previous syndrome extraction round. This lack of hook errors is also thought to be the reason why we obtain α close to 1, preserving the scaling with code distance expected for typical erasures. Delayed erasure checks will be studied more extensively in an upcoming publication (J.D.T., manuscript in preparation).

The data that support the findings of this study are available on Zenodo at https://doi.org/10.5281/zenodo.20433754.

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Author notes

1. Taewan Noh

   Present address: Q-CTRL, Los Angeles, CA, USA

2. Anthony Cabrera

   Present address: NVIDIA Corporation, Santa Clara, CA, USA

3. Jonathan Chen

   Present address: Atom Computing, Berkeley, CA, USA

4. Tzu-Chiao Chien & Anirudh Narla

   Present address: Microsoft Quantum, Redmond, WA, USA

5. Bassel Heiba Elfeky

   Present address: IBM Quantum, Yorktown Heights, NY, USA

6. Nishaad Khedkar

   Present address: Departments of Applied Physics and Physics and Yale Quantum Institute, Yale University, New Haven, CT, USA

7. Tali Shemma

   Present address: Department of Condensed Matter Physics, Weizmann Institute of Science, Rehovot, Israel

8. Teng Zhang

   Present address: Rigetti Computing, Berkeley, CA, USA

9. Olivier Boireau

   Present address: Alice & Bob, Paris, France

10. These authors contributed equally: Nitish Mehta, James D. Teoh, Taewan Noh

Authors and Affiliations

1. D-Wave Quantum Inc., New Haven, CT, USA

   Nitish Mehta, James D. Teoh, Taewan Noh, Ankur Agrawal, Amos Anderson, Beau Birdsall, Avadh Brahmbhatt, Winfred Byrd, Anthony Cabrera, Marc Cacioppo, Leo Carroll, Jonathan Chen, Tzu-Chiao Chien, Richard A. Chamberlin, Jacob C. Curtis, Doreen Danso, Sanjana Renganatha Desigan, Francesco D’Acounto, Bassel Heiba Elfeky, S. M. Farzaneh, Chase Foley, Benjamin Gudlewski, Hannah Hastings, Robert Johnson, Nishaad Khedkar, Trevor Keen, Anup Kumar, Cihan Kurter, Kamila Krawczuk, Eric Langstengel, Richard D. Li, Gangqiang Liu, Hanyi Lu, Pinlei Lu, Luke Mastalli-Kelly, Adam Maines, Michael Maxwell, Heather McCarrick, Mona Mirzaei, Anirudh Narla, Omar Rashad, Erik Reikes, Mizanur Rahman, Rurik Primiani, Michael Schwaller, Ali Sabbah, Tali Shemma, Ruby A. Shi, Sitakanta Satapathy, Dean Stolpe, Jonathan Strenczewilk, Doug Szperka, Iu-Wei Sze, David Sweeney, Preetham Tikkireddi, Chin-Lun Tsung, Daren Vet Sam, Daniel K. Weiss, Zhibo Yang, Liuqi Yu, Teng Zhang, Olivier Boireau, Stephen Horton, Sean Weinberg, José Aumentado, Bryan Cord, Chan U. Lei, Joseph O. Yuan, Shantanu O. Mundhada, Kevin S. Chou, S. Harvey Moseley Jr & Robert J. Schoelkopf

2. Departments of Applied Physics and Physics, Yale University, New Haven, CT, USA

   Robert J. Schoelkopf

3. Yale Quantum Institute, Yale University, New Haven, CT, USA

   Robert J. Schoelkopf

Consortia

Contributions

J.D.T. and S.O.M. contributed to the proposal and concept of the SWS gate. S.O.M. led the design of the dual-rail hardware architecture. J.O.Y. led hardware deployment, experimental setup and system validation. B.C. led the device fabrication. C.U.L. led the cavity design, preparation and testing. K.S.C. led two-qubit gate testing, measurements and analysis. N.M., T.N., P.L., B.H.E., A. Agrawal, A.N., K.S.C, J.O.Y. and J.D.T. contributed to data acquisition and data analysis. T.N., N.M., P.L., A. Agrawal, K.S.C. and J.D.T. contributed to the SWS gate calibration procedure. J.D.T. and K.S.C. contributed to numerical simulations of the SWS gate. P.L., N.M., J.O.Y., T.N., A. Agrawal, B.H.E., G.L., K.S.C. and N.K. contributed to system bring-up and calibration. S.O.M., R.A.C., S.M.F., T.Z., R.D.L., H.M., D.K.W. and J.O.Y. contributed to quantum hardware design and simulation. E.L., B.B., M.C., C.F. and M.R. contributed to mechanical design. S.O.M. and R.A.C. contributed to coupler design and flux-pump delivery. C.U.L., C.K., J.O.Y., B.H.E., A.S. and N.K. contributed to cavity preparation and testing. J.S., A.B., F.D., H.H. and D.V.S. contributed to device assembly and integration. D.D., J.O.Y., M. Maxwell and J.S. contributed to laboratory infrastructure. S.S., M. Mirzaei, D. Stolpe, B. Gudlewski, B.C., H.L., L.Y. and T.Z. performed device fabrication. M. Maxwell, E.R., A.C., S.R.D., R.J., R.P. and O.R. designed, tested and built the radiofrequency control system. J.O.Y., S.O.M., G.L., N.K. and R.A.S. contributed to RF wiring and implementation of the readout chain. J.C.C., P.L., N.M., D.K.W., K.S.C. and T.K. contributed to data analysis of randomized benchmarking results and supporting simulations. J.D.T., S.O.M., A.N., N.M., T.N., K.S.C., H.M., T.-C.C., N.K. and T.S. contributed to an earlier version of the SWS gate. M.S., S.W., D. Sweeney, A. Anderson, W.B., J.C., L.C., A.K., K.K., T.K., A.M., L.M.-K., D. Szperka, I.-W.S., P.T. and Z.Y. contributed to software infrastructure and calibration tools used in this project. K.S.C., N.M., T.N., J.D.T. and R.J.S. wrote the paper. R.J.S., S.H.M., J.A., S.H., O.B. and C.-L.T. managed the project.

Corresponding authors

Correspondence to Nitish Mehta, Kevin S. Chou or Robert J. Schoelkopf.

Competing interests

Authors affiliated with D-Wave Quantum Inc. have financial interest in the company. R.J.S. is a shareholder and consultant for D-Wave Quantum Inc. J.D.T., S.O.M., N.M., K.S.C., T.N., S.H.M. and R.J.S. have filed a provisional patent (application no. PCT/US2025/054681) for the SWS entangling operation.

Peer review information

Nature thanks Pei Zeng and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. Peer reviewer reports are available.

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